QCA7500

QCA7500 Chipset

The QCA7500 HPAV2 Compliant MAC/PHY Transceiver is a System-on-Chip (SoC) designed to bridge multi-stream Ethernet content from a powerline network to an Ethernet 802.3 network. Ex....

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The QCA7500 HPAV2 Compliant MAC/PHY Transceiver is a System-on-Chip (SoC) designed to bridge multi-stream Ethernet content from a powerline network to an Ethernet 802.3 network. Ex....

more

The QCA7500 HPAV2 Compliant MAC/PHY Transceiver is a System-on-Chip (SoC) designed to bridge multi-stream Ethernet content from a powerline network to an Ethernet 802.3 network. Examples include high and standard definition television (HDTV, SDTV), and other digital multimedia file sharing and data applications. The powerline communications (PLC) specific MA....

more

The QCA7500 HPAV2 Compliant MAC/PHY Transceiver is a System-on-Chip (SoC) designed to bridge multi-stream Ethernet content from a powerline network to an Ethernet 802.3 network. Examples include high and standard definition television (HDTV, SDTV), and other digital multimedia file sharing and data applications. The powerline communications (PLC) specific MAC manages network admission and service flows to maximize the quality of service (QoS) over the powerline network.

QCA7500 is a product of Qualcomm Technologies, Inc., and/or its subsidiaries.

Specifications

Ethernet

Ethernet Standards: Home Plug 1.0, IEEE 1905.1, Home Plug AV2, IEEE 1900, IEEE 1901

Ethernet Network: 10/100/1000

Powerline Frequency Bands: 30 MHz, 67.5 MHz

Powerline Configuration: SISO, MIMO

Peak Speed: 1300 Mbps

Security Support

Wi-Fi Security: AES-CCMP, AES-GCMP

Memory

Memory speed: 533MHz, 400MHz

Memory Type: DDR3, DDR2

Flash: 4 MB SPI NOR

Interface

Layers: MAC, PHY

Supported Interfaces: RMII, RGMII, SPI, UART

Input/Output

General Purpose I/Os: 10x

ADC: 1 ADC

DAC: 1 DAC

Package

Package Type: DRQFN

Package Size: 12 x 12 mm

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