QCA7500

QCA7500 is a product of Qualcomm Technologies, Inc.

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QCA7500 Chipset

The QCA7500 HPAV2 Compliant MAC/PHY Transceiver is a System-on-Chip (SoC) designed to bridge multi-stream Ethernet content from a powerline network to an Ethernet 802.3 network. Examples include high and standard definition television (HDTV, SDTV), and other digital multimedia file sharing and data applications. The powerline communications (PLC) specific MAC manages network admission and service flows to maximize the quality of service (QoS) over the powerline network.

QCA7500 Specs

Ethernet

Ethernet Standards

  • IEEE 1905.1
  • Home Plug AV2
  • Home Plug 1.0
  • IEEE 1901
  • IEEE 1900

Powerline Frequency Bands

  • 30 MHz
  • 67.5 MHz

Powerline Configuration

  • SISO
  • MIMO

Ethernet Network

  • 10/100/1000

Peak Speed

  • 1300 Mbps

Security Support

Wi-Fi Security

  • AES-GCMP
  • AES-CCMP

Memory

Memory Speed

  • 533 MHz
  • 400MHz

Memory Type

  • DDR2
  • DDR3

Flash

  • 4 MB SPI NOR

Interface

Layers

  • MAC
  • PHY

Supported Interfaces

  • RMII
  • UART
  • RGMII
  • SPI

Input/Output

ADC

  • 1 ADC

DAC

  • 1 DAC

General Purpose IOs

  • 10

Package

Package Type

  • DRQFN

Package Size

  • 12 x 12 mm