Object Recognition Using Deep Learning Algorithms
University: Kyungpook National University, South Korea
Research Area: Machine Learning
Professor: Giljin Jang
Identifying various kinds of objects using their appearances is one of the key components in the success of the future Smartphone and Internet of Everything business. Most smartphones are equipped with high-resolution video cameras these days, and there are huge number of research outcomes for the object recognition using captured images. Recently, convolutional neural networks with deep learning have shown excellent performance in solving the problem of visual object recognition, utilizing GPGPU (General Purpose Graphic Processing Unit) and stable network learning algorithms. This research aims at understanding the state-of-the-art deep learning technologies for visual object recognition, and propose novel methods to improve the recognition performance. The specific research topics include: (1) modeling statistical dependencies in neighboring image pixels and different convolution kernels, (2) network topology design and learning algorithms to model the proposed statistical dependencies, and (3) efficient implementation of the proposed methods using GPGPU.
On-Die Load-Adaptive Voltage Regulator (VR)
University: Georgia Institute of Technology
Research Area: Processor Architecture & Implementation
Professor: Arijit Raychowdhury
Future energy-efficient processor designs require on-die voltage regulators (VRs) to manage the increasing number of power domains and power states per domain, decreasing decoupling capacitance per local grid, and ultra-wide dynamic range of circuit current load conditions. The design of today’s conventional on-die VRs must target the largest current load condition, resulting in poor energy efficiency at low load conditions. This research focuses on digital load-adaptive low-dropout (LDO) VRs to maximize energy efficiency while maintaining stability at low and high operating voltages. The research explores autonomous and dynamically adaptive VR control loop design to respond to output load changes. Discrete-time and continuous-time topologies as well as hybrid designs are investigated to trade-off response time and stability. This research is validated through the implementation and measurement of a 130nm test-chip. In comparison to a conventional on-die VR, silicon test-chip measurements have demonstrated: (i) 4X current efficiency improvement at light load conditions, (ii) greater than 90% current efficiency across a 50X dynamic load change from 1.15V to 0.45V with a minimum dropout voltage of 50mV, and (iii) 8X improvement in transient response times. Research results are summarized in a paper at the 2015 IEEE International Solid-State Circuits Conference (ISSCC).
Giant Spin Hall Effect (GSHE)
University: Cornell University
Research Area: Emerging memory and logic devices
Professor: Daniel C. Ralph
Spin transfer torque magnetic random access memory (STT-MRAM) is currently positioned as a new class of non-volatile memory due to its high speed, high endurance, logic compatibility, and scalability. Widespread application of such memory will require the development of efficient mechanisms for reorienting their magnetization using the least possible current and power. To maximize the performance and energy efficiency, spin Hall effect (SHE) based programming is gaining traction amongst research and development communities. The application of such mechanism into a practical device would enable MRAM’s utilization in processor low-level caches with programming speeds faster than 1 ns at low energy. Led by the world-renowned research group who discovered the giant spin Hall effect (GSHE) in 2012, this research project evaluates the feasibility of SHE-based memory through materials, device, and memory architecture tuning. A better understanding of programming energy reduction will be established through optimizing device architectures, process integration, and array architectures.
Distinctive Design of Single-ISA Heterogeneous Multi-core Processors
University: North Carolina State University
Research Area: CPU Research
Professor: Eric Rotenberg
A Single-ISA Heterogeneous Multi-core Processor is comprised of multiple core types that implement the same ISA but have different microarchitectures. Different program phases execute on the core type that is most favorable for performance, energy, or a combined metric. Past work considered ensembles of cores that all have the same execution model (superscalar), differing only in their fetch/issue widths, pipeline depths, and sizes of structures. This project explores ensembles of cores that follow different execution models with the same conventional ISA. Hybrids offer tremendous acceleration potential for distinctive program phases. Moreover, by incorporating multiple execution models, the corresponding core types can be simplified and optimized in ways not previously possible.
Qualcomm SWARM Lab at UC Berkeley
University: UC Berkeley
Research Area: Internet of Everything (IoE)
The Swarm Lab at UC Berkeley was started in 2011 with Qualcomm. The lab seeks to foster the creation and distribution of exciting applications of large swarms of sensors and actuators through the adoption of an open and universal platform. A number of Qualcomm projects have strong synergies with the Swarm vision, and are engaged with the lab. These include activities in indoor positioning, Internet of Things, new modes of user interaction with devices around us, novel sensor technologies for gesture recognition, and the Swarm OS. Learn more about the Swarm Lab at UC Berkeley
Fellow-Mentor-Advisor (FMA) Fellowship Program
University: UC San Diego
The Qualcomm Fellow-Mentor-Advisor Fellowship is a 12-month fellowship program for outstanding UCSD Jacobs School of Engineering doctoral students nominated by their Faculty Advisors. The Program brings together teams which include an engineering Ph.D. candidate, his/her faculty advisor and an engineering mentor from Qualcomm. The goal is to foster in-depth connections between the Jacobs School faculty and Qualcomm engineers while enhancing the education of doctoral students. For more information, please visit Jacobs School of Engineering.