Key Research Areas:
• RF Architectures, Antennas, PAs, ICs and Packaging
• Ultra-low Powered Embedded Platforms
• Novel Processor Architectures and Accelerators
• Advanced CMOS R&D
RF Architectures, Antennas, PAs, ICs, and Packaging
Advanced Antenna R&D
5G antennas serve as an essential component for connecting our ASIC (Application-Specific Integrated Circuits) chips to the external wireless world. The system link budget, in conjunction with the ASIC chip capabilities (such as output transmit power and receiver sensitivity levels), provide the necessary information to size the antenna performance. However, the industrial design and mechanical aspects of the host platform pose the most challenging constraints on 5G antenna design. Arriving at the antenna design that meets both electrical and mechanical requirements often requires a unique and innovative antenna solution that is optimized for the specific host device.
Furthermore, support of multiple 5G frequency bands and other wireless technologies (such as 4G, Wi-Fi/BT, 60 GHz WiGig, and GNSS) concurrently is often required in the same host device. This adds even more complexity to the 5G antenna design due to very limited antenna space in typical consumer product devices. Multi-band antenna tuning and multi-mode antenna sharing are examples of our antenna innovations that address these issues. Our engineers continually strive to find the “sweet spot” between minimizing antenna size and maximizing its performance.
Millimeter Wave RF Integrated Circuits (RFIC)
Qualcomm Research is developing RF/analog ASICs to enable next generation wireless technology such as 5G. Recently, we completed development of a mmWave RF front end IC and antenna module in support of requirements for the 5G standard. This marked the industry’s first CMOS 5G mmWave radio optimized for smartphones.
Chip development began with prototyping the system to determine its performance capabilities (range, data rate, etc.) and the required RFIC specifications. Next, we co-designed the phased array transceiver ASIC and antenna module. The antenna module will be integrated into a 5G mmWave prototype radio system later this year and used as a test vehicle for all our 5G specifications and algorithms.
Sub-6 GHz Power Amplifiers (PA)
In addition to mmWave, Qualcomm Research develops 5G PAs for sub-6 GHz. A key challenge for the sub-6GHz 5G PA is achieving wide bandwidth, with tight linearity specifications and sufficient Power-Added Efficiency (PAE). We are creating linearization and coexistence schemes to better manage power consumption. Additionally, we are working to reduce costs, particularly related to calibration.
Advanced RF algorithms
We are also involved in modem-level algorithms as they relate to the radio’s performance within 5G specifications. For example, we are developing digital predistortion (DPD) algorithms specifically targeted to 5G specifications, meeting tough Error Vector Magnitude (EVM) requirements without the large increases in bandwidth typical in DPD. We are also focused on reducing DPD update times by using adaptive algorithms and novel basis functions. Increasing the speed of the DPD algorithm is key so that it can adapt in real-time during a user’s phone call, thereby optimizing battery life, call quality, and system capacity.
Communications Systems Prototyping and Development
We design and develop communication systems prototypes for a variety of communications systems including LTE, 5G-New Radio, Cellular Shared Spectrum, Wi-Fi and satellite communications towards establishing and maintaining our company’s 5G technical leadership including driving standardization of 5G in 3GPP.
To this end, we design advanced prototype platforms and implement end-to-end algorithms (RF, hardware, and software) on those platforms. These are then used to support developing specifications for 5G.
As terrestrial-based communication is reaching its theoretical capacity limits, Qualcomm Research is working with strategic collaborators in the satellite industry to improve satellite-based communication systems. Today’s satellite-based communication systems suffer from slow data rates, long latencies, and expensive user equipment. We are leveraging our extensive knowledge of advance communication systems, state-of-the-art mass produced silicon IP, and when possible, our existing chipsets, to push satellite communications forward, allowing it to deliver a cost-effective user experience on par with terrestrial communications.
Many of the complex systems that we’re developing are industry firsts. Our team must ensure their smooth interaction with the chipset, understand and work with the constraints of existing silicon and adapt it to new waveforms, develop new RF chips to support the new waveforms, and take these technologies into production.
Ultra-low Powered Embedded Platforms
Optimizing for IoT, Voice and Music, Wearables, and Hearables
Qualcomm Research is conducting ultra-low power embedded platform research and development to drive innovations and improvements in IoT, voice and music, wearables, and hearables.
These markets fundamentally have different PPAC (Power, Performance, Area and Cost) envelopes with significantly smaller form factors than smartphones. To achieve this, we focus on developing novel circuits, memories, system architecture, and software that allows us to slash power by at least two orders of magnitude compared to typical mobile SoCs. Combining these technologies with the high level of SoC integration that Qualcomm Research is known for results in a world-class, ultra-low-power platform within a very small form factor. Analyzing and weighing these tradeoffs is the backbone of our research and plays a major role in optimizing the chip’s PPAC.
Our research has revealed that as we lower the platform’s power needs, we can shrink its battery size, which typically comprises approximately 80% of the device’s volume. Thus, as the battery shrinks, the device’s form factor follows. As we continue to drive down the power of these platforms, it opens the possibility to look at alternative energy sources for powering these devices beyond batteries.
We are also researching ultra-low power computer vision. Qualcomm Research is pioneering an Always-on Computer Vision Module (CVM) combining innovations in the system architecture, ultra-low power design and dedicated hardware for vision algorithms running at the “edge”. With low end-to-end power consumption, a tiny form factor and low cost, the CVM can be integrated into a wide range of battery and line-powered devices (IoT, mobile, VR/AR, automotive, etc.), performing object detection, feature recognition, change/motion detection, and other tasks. Its processor performs all computation within the module itself and outputs metadata.
Emerging Semiconductor Memory Technology
Qualcomm Research is pioneering a breakthrough alternative – MRAM (magnetoresistive random-access memory) – a new type of non-volatile working memory which will enable lower system power and lower system cost benefits. For example, MRAM can unify both storage and working memory for a range of IoT applications, which energy efficiency and security are key. MRAM revamps the basic memory structure of the system-on-a-chip. During our MRAM research, we discovered that as the device form factor shrinks, the spin-torque efficiency improves significantly, allowing us to design scalable and lower power MRAM with robust reliability.
We seek to manufacture MRAM using cutting-edge logic processes and are working with our foundry partners to drive our design and architecture efforts to make some key materials and devices tradeoffs.
We are also conducting R&D towards ultra-low power security solutions that are optimized for IoT while leveraging the above technologies.
Novel Processors and Accelerators
Qualcomm Research is committed to advancing the competitiveness of our mobile and data center roadmap. To achieve this, we focus on processor architecture and system optimizations including exploring novel processor architectures, evaluating micro-architectural enhancements and instruction sets, and applying innovative circuit techniques. Our goal is to reduce power, improve performance, and increase the capability of our processors to enable new applications. Our CPU research team also engages with various universities with strong research programs and collaborates closely with the Qualcomm Technologies’ Qualcomm® Snapdragon™ Mobile Platform development team.
The research process begins as we formulate a promising idea for how power can be reduced or performance can be increased. This leads to building models and simulations, followed by building test chips and prototypes.
One of our research breakthroughs is adaptive clock distribution, a way of reducing the voltage that the CPUs need. This minimizes margin, which is extra voltage “padding” applied to the chip to keep it working properly under all conditions. For example, the supply voltage distributed throughout the chip suffers from noise, which can disrupt the circuit functions. The padding offsets the drop and the technique of adaptive clock distribution, allowing us to greatly reduce the amount of margin needed by avoiding the failures that occur in the case of voltage drops. This results in significant power/performance improvement.
Deep Learning Accelerators
Deep Learning algorithms are tremendously compute intensive. The problem we faced is that classical processor architectures are inefficient in delivering the performance, power and area operating points which are desirable for mobile platforms. Additionally, new applications such as augmented reality/virtual reality use algorithms that occupy much of the available compute resources. End-to-end use cases often require concurrent computing on all cores of the SoC – Central Processing Unit (CPU), Graphical Processing Unit (GPU), and Digital Signal Processor (DSP).
Qualcomm Research is developing a specialized deep learning accelerator core that enables the deployment of deep learning techniques concurrently with other resource-intensive applications. This accelerator will offload the brunt of deep learning workloads from the other processors on the SoC, allowing applications to do convolutional and recurrent neural network inference at a higher performance, lower power, and lower area on the SoC.
Advanced CMOS Research
Three-dimensional Integrated Circuit (3D IC) R&D
Traditional CMOS scaling (e.g. 7nm going to 5nm) continues but the wafer manufacturing process is becoming very expensive. We are exploring application of new technologies such as wafer-to-wafer stacking (W2W) or die-to-wafer stacking approaches towards improving performance and power while also enabling stacking different functional units each at an optimal process node.
Alternate Memory Hierarchies
Existing memory hierarchies suggest a memory wall between L3 cache and DRAM and another between DRAM and storage class memory. We are researching alternatives to the existing memory hierarchies including combining novel memory architectures along with innovative IC technologies such as 3D ICs.
Semiconductor Thermal R&D
Chip performance can be limited by thermal aspects such as hot spots. They occur when a high density of localized transistors like those in our graphics-focused DSP run fast and generate heat faster than the heat can be conducted away. Smartphone CPUs today are often ratcheted down to run below rated max speed because of this reason. Qualcomm Research engineers are now working to understand thermal properties of new transistors and interconnect materials used in 7/5nm and beyond. We are working with our foundries and chip design teams to develop thermal simulation models and high performance circuit and memory cells with cooling and layout techniques.
5G Packaging R&D
RF transceivers will soon need to work at extremely high frequency bands, such as 5G mmWave, but will first need to be optimized to reduce sensitivity as any bit of interference or physical motion could disrupt the signals going in and out of the transceiver chip. Additionally, noises generated by the transistor can corrupt or interfere with incoming signals. Qualcomm Research engineers are developing a design technique to isolate noise in our packaging design and are also working with our supply chain on material selection in the build of materials of our 5G packages.
If you find the work we’re doing in ASIC to be exciting, and you have a technical background in ASIC, ultra-low powered embedded platforms, novel processors or accelerators or CMOS, we’d love to hear from you. Please visit us at https://www.qualcomm.com/company/careers to submit your resume’.