How to reduce power consumption on Qualcomm displays by using solid fill planes

Co-written by Jessica Zhang and Abhinav Kumar

This post coincides with a presentation by Jessica Zhang and Abhinav Kumar at X.Org Developers Conference 2023 (XDC 2023). Kumar and Zhang are engineers at the Qualcomm Innovation Center (QUIC).

Display hardware consumes a large share of the power budget. Knowing that developers look for ways to reduce power consumption, we describe an optimization for solid fill planes designed for Qualcomm Technologies hardware.

Solid fill planes have the potential to reduce power consumption by displaying a single-color layer (solid fill) directly to the screen instead of fetching from memory. Currently, the Linux kernel doesn’t expose this capability to users even though some user space compositors, such as the Android hardware composer HAL, support marking specific planes as solid fill. To address this, we’ve posted a patch series that will allow users to take advantage of this optimization to lower power consumption and reduce overhead in specific display use cases.

Solid fill planes and the potential for power savings

The screenshots below show the UI of two common mobile apps:

Currently, this requires a fair bit of power because each layer of the app UI needs to be stored in memory as a framebuffer and fetched by the driver to be displayed on screen.

The Qualcomm® Display Processing Unit (DPU) can use hardware optimizations to reduce power consumption when displaying a single-color (solid fill) layer by skipping this memory fetch step.

In the screenshots above, the shaded areas indicate the parts of the app that can take advantage of the solid fill optimization, thereby potentially reducing power consumption.

Qualcomm Technologies hardware background

The Qualcomm Technologies display pipeline accepts solid color as a valid input for direct rendering manager (DRM) planes. To illustrate how the Qualcomm Technologies display architecture supports the optimization, the diagram below depicts the hardware blocks in the DPU:

• SSPP – Source surface processor pipes
• DSPP – Destination surface processor pipes
• DSI – Display serial interface
• DP – DisplayPort

The SSPP is a hardware block that, in effect, fetches a layer from memory to be displayed onto the screen. For layers that are a single color, it can be programmed to automatically populate a layer with a solid color without the need to fetch from memory.

Implementing the optimization in software

In the “Support for Solid Fill Planes” patch series, we aim to expose these capabilities to userspace by adding two DRM properties and changing the behavior of atomic commits.

First, we have added a “pixel_source” plane property and loosened the atomic commit checks to allow for NULL framebuffers. Currently, the DRM atomic commit call stack requires that the plane have a non-NULL framebuffer that contains the necessary display information (such as format, pixel data, etc.). The new “pixel_source” property and the changes to the atomic commit checks will allow the DRM framework to accept sources of pixel data outside of a framebuffer.

Finally, we introduced a “solid_fill” plane property to the DRM framework. This is a blob type property that will just contain a 32-bit- per- channel RGB value. When the pixel source property is set to “solid_fill” and the solid fill blob property is set with the proper color information, the Qualcomm Technologies display pipeline will be configured to display a solid fill plane without using memory fetch.

The combination of those two properties will disable memory fetch and the resulting plane will display the color specified by the solid_fill blob, as shown in the sequence diagram below:

Potential power savings

The following table summarizes representative power savings from the optimization in the mobile apps shown above:

We use two metrics for power consumption:

• Double-data rate (DDR) Power – The power required to maintain the proper DDR frequency. Power savings come from DDR entering low-power mode when there is no memory fetch.
• Memory Bus Traffic – The traffic between the virtualizing bus interface (VBIF) and DDR.

The “Messenger” and “Chrome” rows represent the regular (without solid fill) levels of current (in mA) and app power (in mW). The rows with the “-split” suffix represent current and app power of the simulated app splitting the display into solid fill and non-solid fill layers.

In these use cases, power savings range from 1% (blue box) to 32% (green box).

Next steps

Have a look at the Support for Solid Fill Planes patches in this series and read through the history of cover letters. And watch our short presentation video, “Enabling Solid Fill Planes,” from XDC 2023.

We hope this optimization sparks interest in and discussion of more driver optimizations for Qualcomm DPU hardware.

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